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--! @file mux.vhd
--! @brief 4-to-1 multiplexer
--! @author Edson S. Gomi (gomi@usp.br)
--! @date 2018-05-02
-------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity mux is
  port (
    I : in std_logic_vector (3 downto 0);
    SEL : in std_logic_vector (1 downto 0);
    Y : out std_logic
    );
end entity mux;

architecture with_select of mux is
begin
  with SEL select
    Y <= I(0) when "00",
         I(1) when "01",
         I(2) when "10",
         I(3) when "11",
    'X' when others;
end architecture with_select;

architecture when_else of mux is
begin
  Y <= I(0) when SEL = "00" else
       I(1) when SEL = "01" else
       I(2) when SEL = "10" else
       I(3) when SEL = "11" else
       'X';
end architecture when_else;

architecture three_state of mux is
begin
  Y <= I(0) when SEL = "00" else 'Z';
  Y <= I(1) when SEL = "01" else 'Z';
  Y <= I(2) when SEL = "10" else 'Z';
  Y <= I(3) when SEL = "11" else 'Z';
end architecture three_state;