-------------------------------------------------------
--! @file dec2to4.vhd
--! @brief Decoder 2 to 4 with enable
--! @author Edson S. Gomi (gomi@usp.br)
--! @date 2018-04-22
-------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity dec2to4 is
  port (
    EN : in std_logic;
    I : in std_logic_vector (1 downto 0);
    Y_L : out std_logic_vector (3 downto 0)
    );
end entity dec2to4;

architecture structural of dec2to4 is
begin
  Y_L(0) <= (I(1) or I(0)) or not(EN);
  Y_L(1) <= (I(1) or not(I(0))) or not(EN);
  Y_L(2) <= (not(I(1)) or I(0)) or not(EN);
  Y_L(3) <= (not(I(1) and I(0))) or not(EN);
end architecture structural;

architecture with_select of dec2to4 is

  signal Z_L : std_logic_vector (3 downto 0);

begin
  
  Y_L <= "1111" when EN = '0' else Z_L;

  with I select         
    Z_L <=
    "1110" when "00",
    "1101" when "01",    
    "1011" when "10",    
    "0111" when "11",    
    "XXXX" when others;  
end architecture with_select;

architecture when_else of dec2to4 is

  signal Z_L : std_logic_vector (3 downto 0);
  
begin
  Y_L <= "1111" when EN = '0' else Z_L;
  
  Z_L <= "1110" when I = "00" else
         "1101" when I = "01" else
         "1011" when I = "10" else 
         "0111" when I = "11" else 
         "XXXX";  
end architecture when_else;