-------------------------------------------------------
--! @file dec2to4_tv.vhd
--! @brief Testbench for the decoder 2 to 4
--! @author Edson S. Gomi (gomi@usp.br)
--! @date 2018-04-22
-------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

--  A testbench has no ports.

entity dec2to4_tb is
end entity dec2to4_tb;

architecture dec2to4_tb_arch of dec2to4_tb is

  --  Declaration of the component that will be instantiated.  
  component dec2to4
    port (
      EN : in std_logic;
      I : in std_logic_vector (1 downto 0); 
      Y_L : out std_logic_vector (3 downto 0)  
    );
  end component;

  signal en : std_logic;
  signal i : std_logic_vector (1 downto 0);
  signal y_l : std_logic_vector (3 downto 0);

begin
  --  Component instantiation.
  decoder: entity work.dec2to4 (structural) port map (
    EN => en,
    I => i,
    Y_L => y_l
    );

  --  This process does the real job.
  stimulus_process: process is
    type pattern_type is record
      --  The inputs of the circuit.
      en : std_logic;
      i : std_logic_vector (1 downto 0);
      
      --  The expected outputs of the circuit.
      y_l : std_logic_vector (3 downto 0);
    end record;

    --  The patterns to apply.
    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
      (('0',"XX","1111"),
       ('1',"00","1110"),
       ('1',"01","1101"),
       ('1',"10","1011"),
       ('1',"11","0111"));

  begin
    --  Initialize inputs.
    --  Nothing to do.
    
    wait for 5 ns;
    
    --  Check each pattern.
    for k in patterns'range loop
      --  Set the inputs.
      en <= patterns(k).en;
      i <= patterns(k).i;
  
  --  Wait for the results.
  wait for 3 ns;
  --  Check the outputs.
  assert y_l = patterns(k).y_l
    report "bad check" severity error;
end loop;
  assert false report "end of test" severity note;
  --  Wait forever; this will finish the simulation.
    wait;
    end process;

end dec2to4_tb_arch;