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--! @file sn74_381.vhd
--! @brief 4-bit Arithmetic Logic Unit
--! @author Edson S. Gomi (gomi@usp.br)
--! @date 2017-11-21
-------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sn74_381 is
  port (
    i_S :   in  std_logic_vector (2 downto 0);  -- Function selector
    i_Cn :  in  std_logic;                      -- Carry in
    i_A :   in  std_logic_vector (3 downto 0);  -- A (4 bits)
    i_B :   in  std_logic_vector (3 downto 0);  -- B (4 bits)
    o_F :   out std_logic_vector (3 downto 0);  -- F (4 bits)
    o_G_L : out std_logic;                      -- Generate G_L
    o_P_L : out std_logic                       -- Propagate P_L
    );
end entity sn74_381;

architecture behavior of sn74_381 is
  signal carry :       unsigned (3 downto 0);         -- Carry 4 bit word
  signal a_plus_b :    std_logic_vector (3 downto 0); -- Sum 4 bits
  signal b_minus_a :   std_logic_vector (3 downto 0); -- Diff 4 bits
  signal a_minus_b :   std_logic_vector (3 downto 0); -- Diff 4 bits
  signal g3,g2,g1,g0 : std_logic;                     -- Carry Generate
  signal p3,p2,p1,p0 : std_logic;                     -- Carry Propagate
  
begin
  carry <= ("000" & i_Cn); -- Carry word initialization

  -- B MINUS A MINUS 1 PLUS Cn
  b_minus_a <= std_logic_vector(unsigned(i_B) + unsigned(not(i_A)) + carry); 

  -- A MINUS B MINUS 1 PLUS Cn
  a_minus_b <= std_logic_vector(unsigned(i_A) + unsigned(not(i_B)) + carry); 

  -- A PLUS B PLUS Cn
  a_plus_b <= std_logic_vector(unsigned(i_A) + unsigned(i_B) + carry);

  with i_S select
    o_F <= (others => '0') when "000", -- F = "0000" 
           b_minus_a       when "001", -- F = B minus A plus Cn
           a_minus_b       when "010", -- F = A minus B plus Cn
           a_plus_b        when "011", -- F = A plus B plus Cn
           i_A xor i_B     when "100", -- F = A xor B
           i_A or i_B      when "101", -- F = A or B
           i_A and i_B     when "110", -- F = A and B
           (others => '1') when "111", -- F = "1111"
           "XXXX"          when others;
  
  g0 <= i_A(0) and i_B(0);
  g1 <= i_A(1) and i_B(1);
  g2 <= i_A(2) and i_B(2);
  g3 <= i_A(3) and i_B(3);

  p0 <= i_A(0) or i_B(0);
  p1 <= i_A(1) or i_B(1);
  p2 <= i_A(2) or i_B(2);
  p3 <= i_A(3) or i_B(3);

  o_G_L <= not(g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and g0));
  o_P_L <= not(p3 and p2 and p1 and p0);
    
end architecture behavior;