-- File : sn74_283_tb.vhd -- Author : Edson S. Gomi -- Version : 1 -- Date : November 2017 library IEEE; use IEEE.std_logic_1164.all; -- A testbench has no ports. entity sn74_283_tb is end entity sn74_283_tb; architecture sn74_283_tb_arch of sn74_283_tb is -- Declaration of the component that will be instantiated. component sn74_283 port ( i_C0 : in std_logic; i_A0 : in std_logic; i_B0 : in std_logic; i_A1 : in std_logic; i_b1 : in std_logic; i_A2 : in std_logic; i_B2 : in std_logic; i_A3 : in std_logic; i_B3 : in std_logic; o_S0 : out std_logic; o_S1 : out std_logic; o_S2 : out std_logic; o_S3 : out std_logic; o_C4 : out std_logic ); end component; signal c0 : std_logic; signal a : std_logic_vector (3 downto 0); signal b : std_logic_vector (3 downto 0); signal s : std_logic_vector (3 downto 0); signal c4 : std_logic; begin -- Component instantiation. adder: entity work.sn74_283 port map ( i_C0 => c0, i_A0 => a(0), i_B0 => b(0), i_A1 => a(1), i_B1 => b(1), i_A2 => a(2), i_B2 => b(2), i_A3 => a(3), i_B3 => b(3), o_S0 => s(0), o_S1 => s(1), o_S2 => s(2), o_S3 => s(3), o_C4 => c4 ); -- This process does the real job. stimulus_process: process is type pattern_type is record -- The inputs of the circuit. c0 : std_logic; a : std_logic_vector (3 downto 0); b : std_logic_vector (3 downto 0); -- The expected outputs of the circuit. s : std_logic_vector (3 downto 0); c4 : std_logic; end record; -- The patterns to apply. type pattern_array is array (natural range <>) of pattern_type; constant patterns : pattern_array := -- (c0, a, b, s, c4) (('0',"0001","0010","0011",'0'), ('1',"0001","0011","0101",'0'), ('0',"0001","1111","0000",'1'), ('1',"0001","1111","0001",'1'), ('1',"1010","0101","0000",'1')); begin -- Check each pattern. for k in patterns'range loop -- Set the inputs. c0 <= patterns(k).c0; a <= patterns(k).a; b <= patterns(k).b; -- Wait for the results. wait for 5 ns; -- Check the outputs. assert s = patterns(k).s report "bad check s" severity error; assert c4 = patterns(k).c4 report "bad check c4" severity error; end loop; assert false report "end of test" severity note; -- Wait forever; this will finish the simulation. wait; end process; end sn74_283_tb_arch;