library IEEE;
use IEEE.std_logic_1164.all;

entity buffer3s is
  port (
    G1_L, G2_L : std_logic;
    A : in std_logic_vector (7 downto 0);
    Y : out std_logic_vector (7 downto 0)
    );
end entity buffer3s;

architecture buffer3s_arch of buffer3s is
begin
  Y <= A when ((G1_L ='0') and (G2_L) = '0') else (others => 'Z');
end architecture buffer3s_arch;