-- Detector de números primos
-- Autor: Edson S. Gomi
-- Versao 1 (Agosto de 2017)


library IEEE;
use IEEE.std_logic_1164.all;

--  A testbench has no ports.

entity prime_tb is
end entity prime_tb;

architecture behav of prime_tb is

  --  Declaration of the component that will be instantiated.  
  component prime 
    port (n3,n2,n1,n0 : in std_logic;
          f : out std_logic);
  end component;

  signal b3,b2,b1,b0 : std_logic := '0';
  signal bout : std_logic := '0';

begin
  --  Component instantiation.
  detector: entity work.prime (prime_maxterms) port map (
    n3 => b3,
    n2 => b2,
    n1 => b1,
    n0 => b0,
    f => bout
    );

  --  This process does the real job.
  stimulus_process: process is
    type pattern_type is record
      --  The inputs of the circuit.
      b3,b2,b1,b0 : std_logic;

      --  The expected outputs of the circuit.
      bout : std_logic;
    end record;


    --  The patterns to apply.
    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
      (('0','0','0','0','0'), -- 0
       ('0','0','0','1','0'), -- 1
       ('0','0','1','0','1'), -- 2 
       ('0','0','1','1','1'), -- 3
       ('0','1','0','0','0'), -- 4
       ('0','1','0','1','1'), -- 5
       ('0','1','1','0','0'), -- 6
       ('0','1','1','1','1'), -- 7 
       ('1','0','0','0','0'), -- 8 
       ('1','0','0','1','0'), -- 9
       ('1','0','1','0','0'), -- 10 
       ('1','0','1','1','1'), -- 11
       ('1','1','0','0','0'), -- 12
       ('1','1','0','1','1'), -- 13
       ('1','1','1','0','0'), -- 14
       ('1','1','1','1','0')); -- 15
 

  begin
    --  Check each pattern.
    for i in patterns'range loop
      --  Set the inputs.
  b0 <= patterns(i).b0;
  b1 <= patterns(i).b1;
  b2 <= patterns(i).b2;
  b3 <= patterns(i).b3;
  --  Wait for the results.
  wait for 5 ns;
  --  Check the outputs.
  assert bout = patterns(i).bout
    report "bad check" severity error;
end loop;
  assert false report "end of test" severity note;
  --  Wait forever; this will finish the simulation.
    wait;
  end process;
  end behav;