# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Altera and sold by Altera or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition
# Date created = 15:09:22  May 03, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		comparador_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE30F23C7
set_global_assignment -name TOP_LEVEL_ENTITY comparador
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.0.0 SP0.01WE"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:09:22  MAY 03, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "15.0.0 SP0.01WE"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_FILE comparador.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_E16 -to a[0]
set_location_assignment PIN_H22 -to a[1]
set_location_assignment PIN_F16 -to a[2]
set_location_assignment PIN_F19 -to a[3]
set_location_assignment PIN_H18 -to b[3]
set_location_assignment PIN_J21 -to b[0]
set_location_assignment PIN_E7 -to igual
set_location_assignment PIN_K21 -to b[1]
set_location_assignment PIN_H20 -to b[2]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top