Two-Input ECL OR Gate With Complementary NOR Output

** Circuit Description **
* dc supplies
Vee1 1  0 DC -5.2V
Vee2 13 0 DC -2.0V
* input digital signals
Va 12 0 DC 0V
Vb 11 0 DC -1.77V
* ECL Gate
Qa 2 12 10 npn_transistor
Qb 2 11 10 npn_transistor
Qr 3  5 10 npn_transistor
Q2 0  3  9 npn_transistor
Q3 0  2  8 npn_transistor
Ra 12 1 50k TC=1200u
Rb 11 1 50k TC=1200u
Re 10 1 779 TC=1200u
Rc1 0 2 220 TC=1200u
Rc2 0 3 245 TC=1200u
Rt2 9 13 50 TC=1200u
Rt3 8 13 50 TC=1200u
* temperature-compensated voltage reference circuit
Q1 0  4 5 npn_transistor
QD1 4 4 6 npn_transistor
QD2 6 6 7 npn_transistor
R1  0 4 907   TC=1200u
R2  7 1 4.98k TC=1200u
R3  5 1 6.1k  TC=1200u
* BJT model statement
.model npn_transistor npn (Is=0.26fA Bf=100 Br=1 
+                          Tf=0.1ns Cje=1pF Cjc=1.5pF Va=100)
** Analysis Requests **
.TEMP 27C
.DC Va -2V 0V 10mV
** Output Requests **
.plot DC V(8) V(9) V(5)
.probe
.end