A CMOS Operational Amplifier (5um CMOS Models)

** Circuit Description **
* power supplies
Vdd 4 0 DC +5V
Vss 5 0 DC -5V
* differential-mode signal level
Vd 101 0 DC 0V
Rd 101 0 1
EVp 2 100 101 0 +0.5
EVm 1 100 101 0 -0.5
* common-mode signal level
Vcm 100 0 DC 0V
* front-end stage
M1 7 1 6 4 pmos_transistor L=8u W=120u
M2 8 2 6 4 pmos_transistor L=8u W=120u
M3 7 7 5 5 nmos_transistor L=10u W=50u
M4 8 7 5 5 nmos_transistor L=10u W=50u
M5 6 9 4 4 pmos_transistor L=10u W=150u
* 2nd gain stage
M6 3 8 5 5 nmos_transistor L=10u W=100u
M7 3 9 4 4 pmos_transistor L=10u W=150u
* current source biasing stage
M8 9 9 4 4 pmos_transistor L=10u W=150u
Iref 9 5 25uA
* compensation network
Cc 8 10 10pF
R 10 3 10k
* 5um BNR CMOS transistor model statements
.MODEL nmos_transistor nmos ( level=2 vto=1 nsub=1e16 tox=8.5e-8 uo=750
+ cgso=4e-10 cgdo=4e-10 cgbo=2e-10 uexp=0.14 ucrit=5e4 vmax=5e4 rsh=15 $ utra -> not used
+ cj=4e-4 mj=2 pb=0.7 cjsw=8e-10 mjsw=2 js=1e-6 xj=1u ld=0.7u )
.MODEL pmos_transistor pmos ( level=2 vto=-1 nsub=2e15 tox=8.5e-8 uo=250
+ cgso=4e-10 cgdo=4e-10 cgbo=2e-10 uexp=0.03 ucrit=1e4 vmax=3e4 rsh=75 $ utra -> not used
+ cj=1.8e-4 mj=2 pb=0.7 cjsw=6e-10 mjsw=2 js=1e-6 xj=0.9u ld=0.6u )
** Analysis Requests **
.DC Vd -4mV +4mV 100uV
** Output Requests **
.PLOT DC V(3)
.probe
.end