A BiCMOS Two-Input Nand Gate

** Circuit Description **
* dc supplies
Vdd 1 0 DC +5V
* input digital signals
Va 6 0 PULSE (0V 5V 0 10ns 10ns 1us 2us) 
Vb 7 0 DC +5V
* CMOS input stage
M1 3 6 1 1 pmos_transistor L=5u W=30u
M2 3 6 4 0 nmos_transistor L=5u W=15u
M3 3 7 1 1 pmos_transistor L=5u W=30u
M4 4 7 5 0 nmos_transistor L=5u W=15u
* Bipolar output stage 
Q5 1 3 2 npn_transistor
Q6 2 5 0 npn_transistor
* High-Swing resistors
R1 5 0 20k
R2 2 3 20k
* Load capacitance 
CL 2 100 5pF IC=+5V
* Capacitor discharge current meter
VCL 100 0 0
* MOS and BJT model statements
.MODEL nmos_transistor nmos ( level=2 vto=1 nsub=1e16 tox=8.5e-8 uo=750             $ convergence problems -> try changing BSIM model level
+ cgso=4e-10 cgdo=4e-10 cgbo=2e-10 uexp=0.14 ucrit=5e4 utra=0 vmax=5e4 rsh=15       $ ngspice: 'utra' parameter not implemented
+ cj=4e-4 mj=2 pb=0.7 cjsw=8e-10 mjsw=2 js=1e-6 xj=1u ld=0.7u )
.MODEL pmos_transistor pmos ( level=2 vto=-1 nsub=2e15 tox=8.5e-8 uo=250            $ convergence problems -> try changing BSIM model level
+ cgso=4e-10 cgdo=4e-10 cgbo=2e-10 uexp=0.03 ucrit=1e4 utra=0 vmax=3e4 rsh=75       $ ngspice: 'utra' parameter not implemented
+ cj=1.8e-4 mj=2 pb=0.7 cjsw=6e-10 mjsw=2 js=1e-6 xj=0.9u ld=0.6u )
.model npn_transistor npn (Is=10fA Bf=100 Br=1 Tf=0.1ns Cje=1pF Cjc=1.5pF Va=100)
** Analysis Requests **
.TRAN 100ns 2.3us 1.8us 100ns UIC
** Output Requests **
.plot TRAN V(2) V(6) I(VCl) 
.probe
.end