A Cascade Of Two ECL Gates Interconnected By A Lossless Transmission Line

* ECL two-input OR/NOR gate
.subckt OR/NOR_ECL   12 11 8 9 1
* connections:        |  | | | |
*                inputA  | | | |
*                   inputB | | |
*                  NORoutput | |
*                     ORoutput |
*                           Vee1
*
* ECL Gate
Qa 2 12 10 npn_transistor
Qb 2 11 10 npn_transistor
Qr 3  5 10 npn_transistor
Q2 0  3  9 npn_transistor
Q3 0  2  8 npn_transistor
Ra 12 1 50k TC=1200u
Rb 11 1 50k TC=1200u
Re 10 1 779 TC=1200u
Rc1 0 2 220 TC=1200u
Rc2 0 3 245 TC=1200u
* temperature-compensated voltage reference circuit
Q1 0  4 5 npn_transistor
QD1 4 4 6 npn_transistor
QD2 6 6 7 npn_transistor
R1  0 4 907   TC=1200u
R2  7 1 4.98k TC=1200u
R3  5 1 6.1k  TC=1200u
* BJT model statement
.model npn_transistor npn (Is=0.26fA Bf=100 Br=1
+                          Tf=0.1ns Cje=1pF Cjc=1.5pF Va=100)
.ends OR/NOR_ECL

** Main Circuit **
* dc supplies
Vee1 5 0 DC -5.2V
Vee2 6 0 DC -2.0V
* input digital signals
Va 1 0 PWL (0,-1.77V 2ns,-1.77V 3ns,-0.884V 30ns,-0.884V)
Vb 2 0 DC -1.77V
* 1st OR/NOR gate: inputB is held low
Xnor_gate1 1 2 3 4 5 OR/NOR_ECL
* 2nd OR/NOR gate: inputB is held low
Xnor_gate2 7 2 8 9 5 OR/NOR_ECL
* transmission line interconnect + terminations 
Tinterconnect 3 0 7 0 Z0=50 Td=10ns
Rt1 7 6 50
Rt2 4 6 50
Rt3 8 6 50
Rt4 9 6 50
** Analysis Requests **
.TRAN 0.05ns 30ns 0s 0.05ns
** Output Requests **
.plot TRAN V(1) V(3) V(7) V(8) 
.probe
.end