Fanout Behavior Of A NAND Gate

* TTL Two-input NAND Gate
.subckt   NAND   10 9 4 1 
* connections:    | | | |
*            inputA | | |
*              inputB | |
*                output |
*                     Vcc
*
Q1a 7 8 10  npn_transistor
Q1b 7 8 9   npn_transistor
Q2  6 7 5   npn_transistor
Q3  4 5 0   npn_transistor
Q4  2 6 3   npn_transistor
QD1 3 3 4   npn_transistor
R1 1 8 4k   TC=1200u
R2 1 6 1.6k TC=1200u
R3 5 0 1k   TC=1200u
R4 1 2 130  TC=1200u
* BJT model statement
.model npn_transistor npn (Is=1.81e-15 Bf=50 Br=0.02 Va=100
+                          Tf=0.1ns Cje=1pF Cjc=1.5pF)
.ends NAND

** Main Circuit **
* dc supplies
Vcc 1 0 DC +5V
* input digital signals
Va 10 0 DC  +2.4; Va=Vohmin
Vb  9 0 DC  +5V
* 1st NAND gate: inputB is held high
Xnand_gate1 10 9 4  1 NAND
* current source load condition
Iload 1 4 0A
** Analysis Requests **
.TEMP 27C
.DC Iload 0A 150mA 1mA
** Output Requests **
.plot DC V(4) xlimit 0 150mA ylimit 0 500mV
.probe
.end