Model { Name "tproflin" Version 4.00 SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off RecordCoverage off CovPath "/" CovSaveName "covdata" CovNameIncrementing off CovHtmlReporting on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Tue Apr 09 16:22:34 2002" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "dansique" ModifiedDateFormat "%" LastModifiedDate "Tue Mar 11 12:42:41 2003" ModelVersionFormat "1.%" ConfigurationManager "none" SimParamPage "Solver" StartTime "0.0" StopTime "1.5" SolverMode "Auto" Solver "ode45" RelTol "1e-3" AbsTol "auto" Refine "1" MaxStep "auto" MinStep "auto" MaxNumMinSteps "-1" InitialStep "auto" FixedStep "auto" MaxOrder 5 OutputOption "RefineOutputTimes" OutputTimes "[]" LoadExternalInput off ExternalInput "[t, u]" SaveTime on TimeSaveName "tout" SaveState off StateSaveName "xout" SaveOutput on OutputSaveName "yout" LoadInitialState off InitialState "xInitial" SaveFinalState off FinalStateName "xFinal" SaveFormat "Array" LimitDataPoints on MaxDataPoints "1000" Decimation "1" AlgebraicLoopMsg "warning" MinStepSizeMsg "warning" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" InheritedTsInSrcMsg "warning" SingleTaskRateTransMsg "none" MultiTaskRateTransMsg "error" IntegerOverflowMsg "warning" CheckForMatrixSingularity "none" UnnecessaryDatatypeConvMsg "none" Int32ToFloatConvMsg "warning" SignalLabelMismatchMsg "none" LinearizationMsg "none" VectorMatrixConversionMsg "none" SfunCompatibilityCheckMsg "none" BlockPriorityViolationMsg "warning" ArrayBoundsChecking "none" ConsistencyChecking "none" ZeroCross on Profile off SimulationMode "normal" RTWSystemTargetFile "grt.tlc" RTWInlineParameters off RTWRetainRTWFile off RTWTemplateMakefile "grt_default_tmf" RTWMakeCommand "make_rtw" RTWGenerateCodeOnly off TLCProfiler off TLCDebug off TLCCoverage off AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" ExtModeMexFile "ext_comm" ExtModeBatchMode off ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeLogAll on OptimizeBlockIOStorage on BufferReuse on ParameterPooling on BlockReductionOpt off BooleanDataType off BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "tproflin" Location [6, 74, 802, 556] Open on ModelBrowserVisibility off ModelBrowserWidth 212 ScreenColor "automatic" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" AutoZoom on ReportName "simulink-default.rpt" Block { BlockType Inport Name "w" Position [15, 98, 45, 112] Port "1" Interpolate on } Block { BlockType Inport Name "u" Position [15, 148, 45, 162] Port "2" Interpolate on } Block { BlockType Mux Name "Mux" Ports [3, 1] Position [675, 173, 685, 247] ShowName off Inputs "3" DisplayOption "bar" } Block { BlockType Sum Name "Sum4" Ports [2, 1] Position [75, 100, 95, 120] ShowName off IconShape "round" Inputs "|+-" SaturateOnIntegerOverflow on } Block { BlockType TransferFcn Name "Transfer Fcn1" Position [390, 82, 450, 118] Numerator "num" Denominator "den" Realization "auto" AbsoluteTolerance "auto" } Block { BlockType TransferFcn Name "w1" Position [200, 17, 260, 53] Numerator "numw1" Denominator "denw1" Realization "auto" AbsoluteTolerance "auto" } Block { BlockType TransferFcn Name "w2" Position [150, 232, 210, 268] Numerator "numw2" Denominator "denw2" Realization "auto" AbsoluteTolerance "auto" } Block { BlockType TransferFcn Name "w3" Position [505, 302, 565, 338] Numerator "numw3" Denominator "denw3" Realization "auto" AbsoluteTolerance "auto" } Block { BlockType Outport Name "z1" Position [715, 203, 745, 217] Port "1" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Outport Name "y" Position [660, 413, 690, 427] Port "2" OutputWhenDisabled "held" InitialOutput "[]" } Line { SrcBlock "Sum4" SrcPort 1 Points [5, 0; 0, -35] Branch { Points [0, -5; 5, 0; 0, -35] DstBlock "w1" DstPort 1 } Branch { Points [540, 0] DstBlock "y" DstPort 1 } } Line { SrcBlock "w" SrcPort 1 Points [0, 5] DstBlock "Sum4" DstPort 1 } Line { SrcBlock "u" SrcPort 1 Points [60, 0] Branch { Points [0, 95] DstBlock "w2" DstPort 1 } Branch { Points [5, 0; 0, -40; 105, 0; 0, -15] DstBlock "Transfer Fcn1" DstPort 1 } } Line { SrcBlock "Transfer Fcn1" SrcPort 1 Points [180, 0; 0, 170; -150, 0; 0, 50] Branch { DstBlock "w3" DstPort 1 } Branch { Points [-400, 0] DstBlock "Sum4" DstPort 2 } } Line { SrcBlock "w1" SrcPort 1 Points [395, 0] DstBlock "Mux" DstPort 1 } Line { SrcBlock "w2" SrcPort 1 Points [440, 0; 0, -40] DstBlock "Mux" DstPort 2 } Line { SrcBlock "w3" SrcPort 1 Points [90, 0] DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "z1" DstPort 1 } } }