MercurioIV DevKit Pin Configuration


Mercurio IV Devkit - Macnica DHW

Pin Assignments:




Pin Assignment Table:



CLOCK
Name Location Direction Standard
CLOCK_50MHz T1 input 3.3-V LVTTL
SMA_CLKIN A12 input 3.3-V LVTTL



SEG7
Name Location Direction Standard
DISP0_D[0] V2 output 3.3-V LVTTL
DISP0_D[1] V1 output 3.3-V LVTTL
DISP0_D[2] U2 output 3.3-V LVTTL
DISP0_D[3] U1 output 3.3-V LVTTL
DISP0_D[4] Y2 output 3.3-V LVTTL
DISP0_D[5] Y1 output 3.3-V LVTTL
DISP0_D[6] W2 output 3.3-V LVTTL
DISP0_D[7] W1 output 3.3-V LVTTL
DISP1_D[0] R5 output 3.3-V LVTTL
DISP1_D[1] T5 output 3.3-V LVTTL
DISP1_D[2] T3 output 3.3-V LVTTL
DISP1_D[3] T4 output 3.3-V LVTTL
DISP1_D[4] M6 output 3.3-V LVTTL
DISP1_D[5] N7 output 3.3-V LVTTL
DISP1_D[6] N6 output 3.3-V LVTTL
DISP1_D[7] P6 output 3.3-V LVTTL



KEY
Name Location Direction Standard
KEY[0] V22 input 3.3-V LVTTL
KEY[1] U20 input 3.3-V LVTTL
KEY[2] U22 input 3.3-V LVTTL
KEY[3] U16 input 3.3-V LVTTL
KEY[4] W20 input 3.3-V LVTTL
KEY[5] U21 input 3.3-V LVTTL
KEY[6] V15 input 3.3-V LVTTL
KEY[7] W17 input 3.3-V LVTTL
KEY[8] W19 input 3.3-V LVTTL
KEY[9] W15 input 3.3-V LVTTL
KEY[10] U17 input 3.3-V LVTTL
KEY[11] Y17 input 3.3-V LVTTL



LED RGB
Name Location Direction Standard
LED_R D7 output 3.3-V LVTTL
LED_G E7 output 3.3-V LVTTL
LED_B D6 output 3.3-V LVTTL



LED MATRIX
Name Location Direction Standard
LEDM_C[0] D7 output 3.3-V LVTTL
LEDM_C[1] E7 output 3.3-V LVTTL
LEDM_C[2] D6 output 3.3-V LVTTL
LEDM_C[3] E7 output 3.3-V LVTTL
LEDM_C[4] D6 output 3.3-V LVTTL
LEDM_R[0] F10 output 3.3-V LVTTL
LEDM_R[1] C8 output 3.3-V LVTTL
LEDM_R[2] E9 output 3.3-V LVTTL
LEDM_R[3] G9 output 3.3-V LVTTL
LEDM_R[4] F9 output 3.3-V LVTTL
LEDM_R[5] F8 output 3.3-V LVTTL
LEDM_R[6] G8 output 3.3-V LVTTL
LEDM_R[7] H11 output 3.3-V LVTTL



SW
Name Location Direction Standard
SW[0] V21 input 3.3-V LVTTL
SW[1] W22 input 3.3-V LVTTL
SW[2] W21 input 3.3-V LVTTL
SW[3] Y22 input 3.3-V LVTTL



VGA
Name Location Direction Standard
VGA_B[0] B14 output 3.3-V LVTTL
VGA_B[1] A15 output 3.3-V LVTTL
VGA_B[2] B15 output 3.3-V LVTTL
VGA_B[3] A16 output 3.3-V LVTTL
VGA_G[0] C13 output 3.3-V LVTTL
VGA_G[1] A13 output 3.3-V LVTTL
VGA_G[2] B13 output 3.3-V LVTTL
VGA_G[3] A14 output 3.3-V LVTTL
VGA_HS B16 output 3.3-V LVTTL
VGA_R[0] A9 output 3.3-V LVTTL
VGA_R[1] C10 output 3.3-V LVTTL
VGA_R[2] A10 output 3.3-V LVTTL
VGA_R[3] B10 output 3.3-V LVTTL
VGA_VS A17 output 3.3-V LVTTL



LCD
Name Location Direction Standard
LCD_RS U9 output 3.3-V LVTTL
LCD_RW U8 output 3.3-V LVTTL
LCD_EN V9 output 3.3-V LVTTL
LCD_D[0] V8 inout 3.3-V LVTTL
LCD_D[1] V7 inout 3.3-V LVTTL
LCD_D[2] V6 inout 3.3-V LVTTL
LCD_D[3] V5 inout 3.3-V LVTTL
LCD_D[4] V4 inout 3.3-V LVTTL
LCD_D[5] Y4 inout 3.3-V LVTTL
LCD_D[6] V3 inout 3.3-V LVTTL
LCD_D[7] Y3 inout 3.3-V LVTTL
LCD_BACKLIGHT V10 output 3.3-V LVTTL



PMOD
Name Location Direction Standard
PROTO_A[0] AB5 inout 3.3-V LVTTL
PROTO_A[1] AB4 inout 3.3-V LVTTL
PROTO_A[2] AB3 inout 3.3-V LVTTL
PROTO_A[3] AA1 inout 3.3-V LVTTL
PROTO_A[4] AA7 inout 3.3-V LVTTL
PROTO_A[5] AA5 inout 3.3-V LVTTL
PROTO_A[6] AA4 inout 3.3-V LVTTL
PROTO_A[7] AA3 inout 3.3-V LVTTL
PROTO_B[0] AB10 inout 3.3-V LVTTL
PROTO_B[1] AB9 inout 3.3-V LVTTL
PROTO_B[2] AB8 inout 3.3-V LVTTL
PROTO_B[3] AB7 inout 3.3-V LVTTL
PROTO_B[4] Y10 inout 3.3-V LVTTL
PROTO_B[5] AA10 inout 3.3-V LVTTL
PROTO_B[6] AA9 inout 3.3-V LVTTL
PROTO_B[7] AA8 inout 3.3-V LVTTL



SDRAM
Name Location Direction Standard
SDRAM_A[0] P2 output 3.3-V LVTTL
SDRAM_A[1] R1 output 3.3-V LVTTL
SDRAM_A[2] P3 output 3.3-V LVTTL
SDRAM_A[3] R2 output 3.3-V LVTTL
SDRAM_A[4] P4 output 3.3-V LVTTL
SDRAM_A[5] P5 output 3.3-V LVTTL
SDRAM_A[6] N5 output 3.3-V LVTTL
SDRAM_A[7] M4 output 3.3-V LVTTL
SDRAM_A[8] N1 output 3.3-V LVTTL
SDRAM_A[9] M2 output 3.3-V LVTTL
SDRAM_A[10] P1 output 3.3-V LVTTL
SDRAM_A[11] M3 output 3.3-V LVTTL
SDRAM_A[12] L6 output 3.3-V LVTTL
SDRAM_BA[0] J4 output 3.3-V LVTTL
SDRAM_BA[1] H2 output 3.3-V LVTTL
SDRAM_CASN M1 output 3.3-V LVTTL
SDRAM_CKE M5 output 3.3-V LVTTL
SDRAM_CLK E5 output 3.3-V LVTTL
SDRAM_CSN H1 output 3.3-V LVTTL
SDRAM_D[0] B2 inout 3.3-V LVTTL
SDRAM_D[1] B1 inout 3.3-V LVTTL
SDRAM_D[2] C2 inout 3.3-V LVTTL
SDRAM_D[3] C1 inout 3.3-V LVTTL
SDRAM_D[4] D2 inout 3.3-V LVTTL
SDRAM_D[5] E3 inout 3.3-V LVTTL
SDRAM_D[6] F2 inout 3.3-V LVTTL
SDRAM_D[7] F1 inout 3.3-V LVTTL
SDRAM_D[8] J2 inout 3.3-V LVTTL
SDRAM_D[9] H6 inout 3.3-V LVTTL
SDRAM_D[10] H5 inout 3.3-V LVTTL
SDRAM_D[11] J3 inout 3.3-V LVTTL
SDRAM_D[12] G3 inout 3.3-V LVTTL
SDRAM_D[13] G4 inout 3.3-V LVTTL
SDRAM_D[14] G5 inout 3.3-V LVTTL
SDRAM_D[15] E4 inout 3.3-V LVTTL
SDRAM_LDQM E1 output 3.3-V LVTTL
SDRAM_RASN N2 output 3.3-V LVTTL
SDRAM_UDQM J5 output 3.3-V LVTTL
SDRAM_WEN J1 output 3.3-V LVTTL