Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
u0|irq_mapper |
4 |
30 |
2 |
30 |
32 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_cmd_width_adapter |
120 |
3 |
0 |
3 |
97 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_rsp_width_adapter|uncompressor |
44 |
4 |
0 |
4 |
35 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_rsp_width_adapter |
102 |
3 |
0 |
3 |
115 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb|adder |
12 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb |
7 |
0 |
4 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001 |
345 |
0 |
0 |
0 |
117 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux|arb|adder |
28 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux|arb |
11 |
0 |
4 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux |
801 |
0 |
0 |
0 |
121 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_006 |
118 |
4 |
2 |
4 |
229 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_005 |
117 |
1 |
2 |
1 |
115 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_004 |
117 |
1 |
2 |
1 |
115 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_003 |
118 |
4 |
2 |
4 |
229 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_002 |
118 |
4 |
2 |
4 |
229 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_001 |
117 |
1 |
2 |
1 |
115 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux |
117 |
1 |
2 |
1 |
115 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_006|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_006|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_006 |
231 |
0 |
0 |
0 |
116 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_005 |
117 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_004 |
117 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003 |
231 |
0 |
0 |
0 |
116 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002 |
231 |
0 |
0 |
0 |
116 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_001 |
117 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux |
117 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux_001 |
125 |
9 |
6 |
9 |
343 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux |
129 |
49 |
2 |
49 |
799 |
49 |
49 |
49 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter |
99 |
3 |
5 |
3 |
97 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_burst_adapter |
99 |
0 |
0 |
0 |
97 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_limiter |
232 |
0 |
0 |
0 |
236 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_limiter |
232 |
0 |
0 |
0 |
236 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_008|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_008 |
92 |
0 |
2 |
0 |
97 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_007|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_007 |
110 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006 |
110 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005 |
110 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004 |
110 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003 |
110 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002 |
110 |
0 |
2 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001 |
110 |
0 |
5 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router |
110 |
0 |
5 |
0 |
115 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_agent_rdata_fifo |
63 |
41 |
0 |
41 |
20 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_agent_rsp_fifo |
132 |
39 |
0 |
39 |
91 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_agent |
231 |
22 |
28 |
22 |
253 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|high_res_timer_s1_agent_rsp_fifo |
150 |
39 |
0 |
39 |
109 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|high_res_timer_s1_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|high_res_timer_s1_agent |
299 |
39 |
44 |
39 |
324 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|led_s1_agent_rsp_fifo |
150 |
39 |
0 |
39 |
109 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|led_s1_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|led_s1_agent |
299 |
39 |
44 |
39 |
324 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_s1_agent_rsp_fifo |
150 |
39 |
0 |
39 |
109 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_s1_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_s1_agent |
299 |
39 |
44 |
39 |
324 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_jtag_debug_module_agent_rsp_fifo |
150 |
39 |
0 |
39 |
109 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_jtag_debug_module_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_jtag_debug_module_agent |
299 |
39 |
44 |
39 |
324 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent_rsp_fifo |
150 |
39 |
0 |
39 |
109 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent |
299 |
39 |
44 |
39 |
324 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo |
150 |
39 |
0 |
39 |
109 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent |
299 |
39 |
44 |
39 |
324 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_agent |
188 |
37 |
82 |
37 |
142 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_agent |
188 |
37 |
82 |
37 |
142 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cfi_flash_uas_translator |
76 |
4 |
2 |
4 |
68 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|high_res_timer_s1_translator |
95 |
22 |
44 |
22 |
55 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|led_s1_translator |
111 |
6 |
29 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_s1_translator |
111 |
7 |
12 |
7 |
89 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_jtag_debug_module_translator |
111 |
5 |
19 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_translator |
111 |
6 |
27 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator |
111 |
5 |
30 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_translator |
112 |
51 |
2 |
51 |
105 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_translator |
112 |
12 |
2 |
12 |
105 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0 |
294 |
0 |
0 |
0 |
315 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|tri_state_bridge_flash_pinsharer_flash|arbiter|arb|adder |
4 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|tri_state_bridge_flash_pinsharer_flash|arbiter|arb |
4 |
0 |
3 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|tri_state_bridge_flash_pinsharer_flash|arbiter |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|tri_state_bridge_flash_pinsharer_flash|pin_sharer |
67 |
0 |
0 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|tri_state_bridge_flash_pinsharer_flash |
66 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|sysid_qsys |
3 |
16 |
2 |
16 |
32 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2|the_altsyncram|auto_generated|mux2 |
227 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2|the_altsyncram|auto_generated|decode3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2|the_altsyncram|auto_generated |
55 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2 |
58 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|nios2_qsys |
151 |
0 |
30 |
0 |
130 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|led |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0|high_res_timer |
23 |
0 |
15 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|flash_tri_state_bridge |
49 |
0 |
0 |
0 |
46 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
u0|cfi_flash|tda |
79 |
13 |
1 |
13 |
64 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|cfi_flash|slave_translator |
74 |
6 |
0 |
6 |
63 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|cfi_flash|tdt |
71 |
1 |
1 |
1 |
70 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|cfi_flash |
69 |
0 |
0 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0 |
2 |
1 |
0 |
1 |
37 |
1 |
1 |
1 |
16 |
0 |
0 |
0 |
0 |