library IEEE;
use IEEE.std_logic_1164.all;

--  A testbench has no ports.

entity v74x138_tb is
end entity v74x138_tb;

architecture v74x138_tb_arch of v74x138_tb is

  --  Declaration of the component that will be instantiated.  
  component v74x138
                  port ( G1, G2A_L, G2B_L : in std_logic;
                         A : in std_logic_vector (2 downto 0);
                         Y_L : out std_logic_vector (0 to 7));                
  end component;

  signal g1, g2a_l, g2b_l : std_logic;
  signal a : std_logic_vector (2 downto 0);
  signal y_l : std_logic_vector (0 to 7);

begin
  --  Component instantiation.
  decoder: entity work.v74x138 port map (
    G1 => g1,
    G2A_L => g2a_l,
    G2B_L => g2b_l,
    A => a,
    Y_L => y_l
    );

  --  This process does the real job.
  stimulus_process: process is
    type pattern_type is record
      --  The inputs of the circuit.
      g1, g2a_l, g2b_l : std_logic;
      a : std_logic_vector (2 downto 0);
      
      --  The expected outputs of the circuit.
      y_l : std_logic_vector (0 to 7);
    end record;


    --  The patterns to apply.
    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
      (('1','0','0',"000","01111111"),
       ('0','0','0',"000","11111111"),
       ('1','1','0',"000","11111111"),
       ('1','0','1',"000","11111111"),
       ('1','0','0',"000","01111111"),
       ('1','0','0',"001","10111111"),
       ('1','0','0',"010","11011111"),
       ('1','0','0',"011","11101111"),
       ('1','0','0',"100","11110111"),
       ('1','0','0',"101","11111011"),
       ('1','0','0',"110","11111101"),
       ('1','0','0',"111","11111110"),
       ('1','0','0',"000","01111111"));

  begin
    --  Initialize inputs.
    g1 <= '0';
    g2a_l <= '1';
    g2b_l <= '1';
    a <= "111";

    wait for 5 ns;
    
    --  Check each pattern.
    for i in patterns'range loop
      --  Set the inputs.
  g1 <= patterns(i).g1;
  g2a_l <= patterns(i).g2a_l;
  g2b_l <= patterns(i).g2b_l;
  a <= patterns(i).a;
  
  --  Wait for the results.
  wait for 3 ns;
  --  Check the outputs.
  assert y_l = patterns(i).y_l
    report "bad check" severity error;
end loop;
  assert false report "end of test" severity note;
  --  Wait forever; this will finish the simulation.
    wait;
    end process;
    
end v74x138_tb_arch;