-------------------------------------------------------
--! @file dec3to8.vhd
--! @brief Testbench for the decoder 3 to 8
--! @author Edson S. Gomi (gomi@usp.br)
--! @date 2018-04-23
-------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;

--  A testbench has no ports.

entity dec3to8_tb is
end entity dec3to8_tb;

architecture dec3to8_tb_arch of dec3to8_tb is

  --  Declaration of the component that will be instantiated.  
  component dec3to8
                  port ( G1, G2A_L, G2B_L : in std_logic;
                         DIN : in std_logic_vector (2 downto 0);
                         Z_L : out std_logic_vector (7 downto 0));                
  end component;

  signal g1, g2a_l, g2b_l : std_logic;
  signal din : std_logic_vector (2 downto 0);
  signal z_l : std_logic_vector (7 downto 0);

begin
  --  Component instantiation.
  decoder: entity work.dec3to8 (structural) port map (
    G1 => g1,
    G2A_L => g2a_l,
    G2B_L => g2b_l,
    DIN => din,
    Z_L => z_l
    );

  --  This process does the real job.
  stimulus_process: process is
    type pattern_type is record
      --  The inputs of the circuit.
      g1, g2a_l, g2b_l : std_logic;
      din : std_logic_vector (2 downto 0);
      
      --  The expected outputs of the circuit.
      z_l : std_logic_vector (7 downto 0);
    end record;


    --  The patterns to apply.
    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
      (('1','0','0',"000","11111110"),
       ('0','0','0',"000","11111111"),
       ('1','1','0',"000","11111111"),
       ('1','0','1',"000","11111111"),
       ('1','0','0',"000","11111110"),
       ('1','0','0',"001","11111101"),
       ('1','0','0',"010","11111011"),
       ('1','0','0',"011","11110111"),
       ('1','0','0',"100","11101111"),
       ('1','0','0',"101","11011111"),
       ('1','0','0',"110","10111111"),
       ('1','0','0',"111","01111111"),
       ('1','0','0',"000","11111110"));

  begin
    --  Initialize inputs.
    g1 <= '0';
    g2a_l <= '1';
    g2b_l <= '1';
    din <= "111";

    wait for 5 ns;
    
    --  Check each pattern.
    for i in patterns'range loop
      --  Set the inputs.
  g1 <= patterns(i).g1;
  g2a_l <= patterns(i).g2a_l;
  g2b_l <= patterns(i).g2b_l;
  din <= patterns(i).din;
  
  --  Wait for the results.
  wait for 3 ns;
  --  Check the outputs.
  assert z_l = patterns(i).z_l
    report "bad check" severity error;
end loop;
  assert false report "end of test" severity note;
  --  Wait forever; this will finish the simulation.
    wait;
    end process;
    
end dec3to8_tb_arch;