Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
u0|irq_mapper |
3 |
31 |
2 |
31 |
32 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001 |
211 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux|arb|adder |
20 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux|arb |
9 |
0 |
4 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux |
523 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_004 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_003 |
108 |
4 |
2 |
4 |
209 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_002 |
108 |
4 |
2 |
4 |
209 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_001 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_004 |
107 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003 |
211 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002 |
211 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_001 |
107 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux |
107 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux_001 |
112 |
4 |
5 |
4 |
209 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux |
115 |
25 |
2 |
25 |
521 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_limiter |
212 |
0 |
0 |
0 |
214 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_limiter |
212 |
0 |
0 |
0 |
214 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006 |
102 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005 |
102 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004 |
102 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003 |
102 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002 |
102 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001 |
102 |
0 |
5 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router |
102 |
0 |
5 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|led_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|led_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|led_s1_agent |
281 |
39 |
42 |
39 |
300 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_s1_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_s1_agent |
281 |
39 |
42 |
39 |
300 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_jtag_debug_module_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_jtag_debug_module_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_jtag_debug_module_agent |
281 |
39 |
42 |
39 |
300 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent |
281 |
39 |
42 |
39 |
300 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo |
142 |
39 |
0 |
39 |
101 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent |
281 |
39 |
42 |
39 |
300 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_agent |
170 |
37 |
72 |
37 |
134 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_agent |
170 |
37 |
72 |
37 |
134 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|led_s1_translator |
103 |
6 |
21 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_s1_translator |
103 |
7 |
4 |
7 |
89 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_jtag_debug_module_translator |
103 |
5 |
11 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_translator |
103 |
6 |
19 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator |
103 |
5 |
22 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_translator |
104 |
51 |
2 |
51 |
97 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_translator |
104 |
12 |
2 |
12 |
97 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0 |
244 |
0 |
0 |
0 |
244 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|sysid_qsys |
3 |
16 |
2 |
16 |
32 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2|the_altsyncram|auto_generated|mux2 |
227 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2|the_altsyncram|auto_generated|decode3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2|the_altsyncram|auto_generated |
55 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2 |
58 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|nios2_qsys |
151 |
0 |
31 |
0 |
114 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|led |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_DE2i_150_QSYS_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0 |
2 |
1 |
0 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |