-- File : sn74_999_tb.vhd
-- Author : Edson S. Gomi
-- Version : 1
-- Date : November 2017

library IEEE;
use IEEE.std_logic_1164.all;

--  A testbench has no ports.

entity sn74_999_tb is
end entity sn74_999_tb;

architecture sn74_999_tb_arch of sn74_999_tb is

  --  Declaration of the component that will be instantiated.  
  component sn74_999
    port (
      BIN : in std_logic;
      X : in std_logic_vector (3 downto 0);
      Y : in std_logic_vector (3 downto 0);
      D : out std_logic_vector (3 downto 0);
      BOUT : out std_logic
    );
  end component;

  signal bin : std_logic;
  signal x : std_logic_vector (3 downto 0);
  signal y : std_logic_vector (3 downto 0);
  signal d : std_logic_vector (3 downto 0);
  signal bout : std_logic;
  
begin
  --  Component instantiation.
  subtractor: entity work.sn74_999 port map (
    BIN => bin,
    X => x,
    Y => y,
    D => d,
    BOUT => bout
    );
  
  --  This process does the real job.
  stimulus_process: process is
    type pattern_type is record
      --  The inputs of the circuit.
   bin : std_logic;
   x : std_logic_vector (3 downto 0);
   y : std_logic_vector (3 downto 0);
       
      --  The expected outputs of the circuit.
   d : std_logic_vector (3 downto 0);
   bout : std_logic;

 
    end record;

    --  The patterns to apply.
    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
    -- (bin_l, X, Y, D, bout_l)
      (('0',"0001","0010","1111",'1'),
       ('1',"0001","0010","1110",'1'),
       ('0',"0000","1111","0001",'1'),
       ('1',"0000","1111","0000",'1'),
       ('1',"1010","0101","0100",'0'));
       
  begin
    
    --  Check each pattern.
    for k in patterns'range loop
      --  Set the inputs.
      bin <= patterns(k).bin;
      x <= patterns(k).x;
      y <= patterns(k).y;

      --  Wait for the results.
  wait for 5 ns;
  
  --  Check the outputs.
      assert d = patterns(k).d
        report "bad check d" severity error;
      assert bout = patterns(k).bout
        report "bad check bout" severity error;
    end loop;
    
  assert false report "end of test" severity note;
  --  Wait forever; this will finish the simulation.
    wait;
    end process;
    
end sn74_999_tb_arch;