-- File : sn74_85.vhd
-- 4-bit magnitude comparator
-- Author : Edson S. Gomi
-- Version : 1
-- Date : November 2017

library IEEE;
use IEEE.std_logic_1164.all;

entity sn74_85 is
  port (
    i_A3 : in std_logic;
    i_B3 : in std_logic;
    i_A2 : in std_logic;
    i_B2 : in std_logic;
    i_A1 : in std_logic;
    i_B1 : in std_logic;
    i_A0 : in std_logic;
    i_B0 : in std_logic;
    i_AGTB : in std_logic;
    i_ALTB : in std_logic;
    i_AEQB : in std_logic;
    o_AGTB : out std_logic;
    o_ALTB : out std_logic;
    o_AEQB : out std_logic
    );
end entity sn74_85;

architecture sn74_85_arch of sn74_85 is
  signal agtb : std_logic;
  signal aeqb : std_logic;
  signal altb : std_logic;
begin
  -- Wakerly, J.F. Digital Design - Principles and Practice 4th Edition
  -- Equations from Chapter 6, page 462
  -- See also SN7485 Function Table 
  agtb <= (i_A3 and not(i_B3)) or
          (not(i_A3 xor i_B3) and i_A2 and not(i_B2)) or
          (not(i_A3 xor i_B3) and not(i_A2 xor i_B2) and i_A1 and not(i_B1)) or
          (not(i_A3 xor i_B3) and not(i_A2 xor i_B2) and not(i_A1 xor i_B1) and i_A0 and not(i_B0));
  aeqb <= not((i_A3 xor i_B3) or (i_A2 xor i_B2) or (i_A1 xor i_B1) or (i_A0 xor i_B0));
  altb <= not(agtb or aeqb);
  o_AGTB <= agtb or (aeqb and (not(i_AEQB) and not(i_ALTB)));
  o_ALTB <= altb or (aeqb and (not(i_AEQB) and not(i_AGTB)));
  o_AEQB <= aeqb and i_AEQB;
  
end sn74_85_arch;