-- File : sn74_280.vhd -- Author : Edson S. Gomi -- Version : 1 -- Date : October 2017 library IEEE; use IEEE.std_logic_1164.all; entity sn74_280 is port ( i_A : in std_logic; i_B : in std_logic; i_C : in std_logic; i_D : in std_logic; i_E : in std_logic; i_F : in std_logic; i_G : in std_logic; i_H : in std_logic; i_I : in std_logic; o_EVEN : out std_logic; o_ODD : out std_logic ); end entity sn74_280; architecture sn74_280_arch of sn74_280 is signal o_odd_internal : std_logic; begin o_odd_internal <= (((i_A xor i_B) xor (i_C xor i_D)) xor ((i_E xor i_F) xor (i_G xor i_H))) xor i_I; o_ODD <= o_odd_internal; o_EVEN <= not(o_odd_internal); end architecture sn74_280_arch;