-- File : parity9.vhd
-- Author : Wakerly 4th Edition
-- Date : October 2017

library IEEE;
use IEEE.std_logic_1164.all;

entity parity9 is
  port (
    I : in std_logic_vector (8 downto 0);
    EVEN, ODD : out std_logic
    );
end entity parity9;

architecture parity9b of parity9 is
begin
  process (I)
    variable p : std_logic;
  begin
    p := I(0);
    for j in 1 to 8 loop
      if I(j) = '1' then
        p := not p;
      end if;
    end loop;
    ODD <= p;
    EVEn <= not p;
  end process;
end architecture parity9b;

architecture parity9s of parity9 is
  component vxor3
    port (
      A, B, C : in std_logic;
      Y : out std_logic
      );
  end component;
  signal Y1, Y2, Y3, Y3N : std_logic;
begin
  U1 : vxor3 port map (I(0), I(1), I(2), Y1);
  U2 : vxor3 port map (I(3), I(4), I(5), Y2);
  U3 : vxor3 port map (I(6), I(7), I(8), Y3);
  Y3N <= not Y3;
  U4 : vxor3 port map (Y1, Y2, Y3, ODD);
  U5 : vxor3 port map (Y1, Y2, Y3N, EVEN);
end architecture parity9s;