library IEEE; use IEEE.std_logic_1164.all; entity hamming is port ( DU : in std_logic_vector (1 to 7); DC : out std_logic_vector (1 to 7); NOERROR : out std_logic ); end entity hamming; architecture hamming_arch of hamming is component sn74_280 is port ( i_A : in std_logic; i_B : in std_logic; i_C : in std_logic; i_D : in std_logic; i_E : in std_logic; i_F : in std_logic; i_G : in std_logic; i_H : in std_logic; i_I : in std_logic; o_EVEN : out std_logic; o_ODD : out std_logic ); end component; component sn74_138 is port ( i_G1 : in std_logic; i_G2A_L : in std_logic; i_G2B_L : in std_logic; i_A : in std_logic; i_B : in std_logic; i_C : in std_logic; o_Y0_L : out std_logic; o_Y1_L : out std_logic; o_Y2_L : out std_logic; o_Y3_L : out std_logic; o_Y4_L : out std_logic; o_Y5_L : out std_logic; o_Y6_L : out std_logic; o_Y7_L : out std_logic ); end component; component sn74_86 is port ( i_1A : in std_logic; i_1B : in std_logic; i_2A : in std_logic; i_2B : in std_logic; i_3A : in std_logic; i_3B : in std_logic; i_4A : in std_logic; i_4B : in std_logic; o_1Y : out std_logic; o_2Y : out std_logic; o_3Y : out std_logic; o_4Y : out std_logic ); end component; signal SYN0, SYN1, SYN2 : std_logic; signal E0_L,E1_L,E2_L,E3_L,E4_L,E5_L,E6_L,E7_L : std_logic; signal DC_L1,DC_L2,DC_L3,DC_L4,DC_L5,DC_L6,DC_L7 : std_logic; signal dc_l_internal : std_logic_vector (1 to 7); begin parityA : component sn74_280 port map (DU(7),DU(5),DU(3),DU(1),'0','0','0','0','0',open,SYN0); parityB : component sn74_280 port map (DU(7),DU(6),DU(3),DU(2),'0','0','0','0','0',open,SYN1); parityC : component sn74_280 port map (DU(7),DU(6),DU(5),DU(4),'0','0','0','0','0',open,SYN2); decoder : component sn74_138 port map ('1','0','0',SYN0,SYN1,SYN2,E0_L,E1_L,E2_L,E3_L,E4_L,E5_L,E6_L,E7_L); xor1 : component sn74_86 port map (DU(1),E1_L,DU(2),E2_L,DU(3),E3_L,DU(4),E4_L,DC_L1,DC_L2,DC_L3,DC_L4); xor2 : component sn74_86 port map (DU(5),E5_L,DU(6),E6_L,DU(7),E7_L,'0','0',DC_L5,DC_L6,DC_L7,open); dc_l_internal <= DC_L1 & DC_L2 & DC_L3 & DC_L4 & DC_L5 & DC_L6 & DC_L7; DC <= not(dc_l_internal); NOERROR <= not(E0_L); end architecture hamming_arch;