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--! @file sn74_182.vhd
--! @brief Look-ahead Carry Generator
--! @author Edson S. Gomi (gomi@usp.br)
--! @date 2017-11-22
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sn74_182 is
  port (
    i_C0 : in std_logic;
    i_G0_L : in std_logic;
    i_P0_L : in std_logic;
    i_G1_L : in std_logic;
    i_P1_L : in std_logic;
    i_G2_L : in std_logic;
    i_P2_L : in std_logic;
    i_G3_L : in std_logic;
    i_P3_L : in std_logic;
    o_C1 : out std_logic;
    o_C2 : out std_logic;
    o_C3 : out std_logic;
    o_G_L : out std_logic;
    o_P_L : out std_logic
    );
end entity sn74_182;

architecture sn74_182_arch of sn74_182 is
  signal g0, g1, g2, g3 : std_logic;
  signal p0, p1, p2, p3 : std_logic;
begin
  g0 <= not(i_G0_L);
  g1 <= not(i_G1_L);
  g2 <= not(i_G2_L);
  g3 <= not(i_G3_L);
  p0 <= not(i_P0_L);
  p1 <= not(i_P1_L);
  p2 <= not(i_P2_L);
  p3 <= not(i_P3_L);
  
  o_C1 <= (g0 or p0) and (g0 or i_C0);
  o_C2 <= (g1 or p1) and (g1 or g0 or p0) and (g1 or g0 or i_C0);
  o_C3 <= (g2 or p2) and (g2 or g1 or p1) and (g2 or g1 or g0 or p0) and (g2 or g1 or g0 or i_C0);

  o_G_L <= not((g3 or p3) and (g3 or g2 or p2) and (g3 or g2 or g1 or p1) and (g3 or g2 or g1 or g0));
  o_P_L <= not(p0 and p1 and p2 and p3);
  
end architecture sn74_182_arch;