-- File : sn74_181_tb.vhd -- Testbench for Active High and Low Data -- Author : Edson S. Gomi -- Version : 1 -- Date : November 2017 library IEEE; use IEEE.std_logic_1164.all; -- A testbench has no ports. entity sn74_181_tb is end entity sn74_181_tb; architecture sn74_181_tb_arch of sn74_181_tb is -- Declaration of the component that will be instantiated. component sn74_181 port ( i_S3 : in std_logic; i_S2 : in std_logic; i_S1 : in std_logic; i_S0 : in std_logic; i_A3_L : in std_logic; i_A2_L : in std_logic; i_A1_L : in std_logic; i_A0_L : in std_logic; i_B3_L : in std_logic; i_B2_L : in std_logic; i_B1_L : in std_logic; i_B0_L : in std_logic; i_M : in std_logic; i_Cn : in std_logic; o_F3_L : out std_logic; o_F2_L : out std_logic; o_F1_L : out std_logic; o_F0_L : out std_logic; o_G_L : out std_logic; o_Cn4 : out std_logic; o_P_L : out std_logic; o_AEQB : out std_logic ); end component; signal S : std_logic_vector (3 downto 0); signal A : std_logic_vector (3 downto 0); signal B : std_logic_vector (3 downto 0); signal F : std_logic_vector (3 downto 0); signal M : std_logic; signal Cn_L : std_logic; signal G : std_logic; signal Cn4_L : std_logic; signal P : std_logic; signal AEQB_L : std_logic; begin -- Component instantiation. alu: entity work.sn74_181 port map ( i_S3 => S(3), i_S2 => S(2), i_S1 => S(1), i_S0 => S(0), i_A3_L => A(3), i_A2_L => A(2), i_A1_L => A(1), i_A0_L => A(0), i_B3_L => B(3), i_B2_L => B(2), i_B1_L => B(1), i_B0_L => B(0), i_M => M, i_Cn => Cn_L, o_F3_L => F(3), o_F2_L => F(2), o_F1_L => F(1), o_F0_L => F(0), o_G_L => G, o_Cn4 => Cn4_L, o_P_L => P, o_AEQB => AEQB_L ); -- This process does the real job. stimulus_process: process is type pattern_type is record -- The inputs of the circuit. S : std_logic_vector(3 downto 0); A : std_logic_vector(3 downto 0); B : std_logic_vector(3 downto 0); Cn_L : std_logic; M : std_logic; -- The expected outputs of the circuit. F : std_logic_vector(3 downto 0); G : std_logic; P : std_logic; Cn4_L : std_logic; AEQB_L : std_logic; end record; -- The patterns to apply. type pattern_array is array (natural range <>) of pattern_type; constant patterns : pattern_array := -- ( S, A, B, Cn_L, M, F, G, P,Cn4_L,AEQB_L) ( -- Arithmetic Functions ("0000","1010","0101",'0','0',"1011",'0','0','1','0'), -- F = A PLUS 1 -- F = A MINUS 1 ("0011","1010","0101",'1','0',"1111",'1','0','0','1'), -- F = -1 (2's complement) -- F = 0 (2's complement) ("0110","0000","0001",'0','0',"1111",'0','0','1','1'), -- F = A MINUS B -- F = A MINUS B MINUS 1 ("1001","1110","0011",'1','0',"0001",'1','1','1','0'), -- F = A PLUS B -- F = A PLUS B PLUS 1 ("1100","1111","1111",'1','0',"1110",'1','1','1','0'), -- F = A PLUS A -- F = A PLUS A PLUS 1 ("1111","0000","0001",'1','0',"1111",'1','0','0','1'), -- F = A MINUS 1 -- F = A PLUS 1 -- Logic Functions ("0000","1010","0101",'1','1',"0101",'0','0','1','0'), -- F = not(A) -- F = not(A) ("0001","1010","0101",'1','1',"0000",'1','0','0','0'), -- F = not(A+B) -- F = not(A.B) ("0010","1010","0101",'1','1',"0101",'0','0','1','0'), -- F = not(A).B -- F = not(A)+B ("0011","1010","0101",'1','1',"0000",'1','0','0','0'), -- F = 0 -- F = 1 ("0100","1010","0101",'1','1',"1111",'1','1','1','1'), -- F = not(A.B) -- F = not(A+B) ("0101","1010","0101",'1','1',"1010",'1','1','1','0'), -- F = not(B) -- F = not(B) ("0110","1010","0101",'1','1',"1111",'1','1','1','1'), -- F = A xor B -- F = not(A) xnor not(B) ("0111","1010","0101",'1','1',"1010",'1','1','1','0'), -- F = A.not(B) -- F = A+B ("1000","1010","0101",'1','1',"0101",'0','0','1','0'), -- F = not(A)+B -- F = not(A).B ("1001","1010","0101",'1','1',"0000",'1','0','0','0'), -- F = not(A) xnor not(B) -- F = A xor B ("1010","1010","0101",'1','1',"0101",'0','0','1','0'), -- F = B -- F = B ("1011","1010","0101",'1','1',"0000",'1','0','0','0'), -- F = A.B -- F = A+B ("1100","1010","0101",'1','1',"1111",'1','1','1','1'), -- F = 1 -- F = 0 ("1101","1010","0101",'1','1',"1010",'1','1','1','0'), -- F = A+not(B) -- F = A.not(B) ("1110","1010","0101",'1','1',"1111",'1','1','1','1'), -- F = A+B -- F = A.B ("1111","1010","0101",'1','1',"1010",'1','1','1','0'));-- F = A -- F = A begin -- Check each pattern. for k in patterns'range loop -- Set the inputs. S <= patterns(k).S; A <= patterns(k).A; B <= patterns(k).B; Cn_L <= patterns(k).Cn_L; M <= patterns(k).M; -- Wait for the results. wait for 5 ns; -- Check the outputs. assert F = patterns(k).F report "bad check F_L" severity error; assert G = patterns(k).G report "bad check G_L" severity error; assert P = patterns(k).P report "bad check P_L" severity error; assert Cn4_L = patterns(k).Cn4_L report "bad check Cn4" severity error; assert AEQB_L = patterns(k).AEQB_L report "bad check AEQB" severity error; end loop; assert false report "end of test" severity note; -- Wait forever; this will finish the simulation. wait; end process; end sn74_181_tb_arch;