------------------------------------------------------- --! @file ha.vhd --! @brief half adder --! @author Bruno Albertini (balbertini@usp.br) --! @date 2017-11-13 ------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity ha is port ( a, b : in std_logic; r, co : out std_logic ); end entity; architecture structural of ha is begin r <= a xor b; co <= (a and b); end architecture;