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--! @file fa.vhd
--! @brief full adder
--! @author Bruno Albertini (balbertini@usp.br)
--! @date 2017-11-13
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library ieee;
use ieee.std_logic_1164.all;

entity fa is
  port (
    a, b, ci : in  std_logic;
    r, co : out std_logic
  );
end entity;

architecture structural of fa is
begin
  r <= a xor b xor ci;
  co <= (a and b) or (a and ci) or (b and ci);
end architecture;