-- File : sn74_283.vhd
-- 4-bit binary full adder with carry
-- Author : Edson S. Gomi
-- Version : 1
-- Date : November 2017

library IEEE;
use IEEE.std_logic_1164.all;

entity sn74_283 is
  port (
    i_C0 : in std_logic;
    i_A0 : in std_logic;
    i_B0 : in std_logic;
    i_A1 : in std_logic;
    i_b1 : in std_logic;
    i_A2 : in std_logic;
    i_B2 : in std_logic;
    i_A3 : in std_logic;
    i_B3 : in std_logic;
    o_S0 : out std_logic;
    o_S1 : out std_logic;
    o_S2 : out std_logic;
    o_S3 : out std_logic;
    o_C4 : out std_logic
    );
end entity sn74_283;

architecture sn74_283_arch of sn74_283 is
  signal c0 : std_logic;
  signal c1 : std_logic;
  signal c2 : std_logic;
  signal c3 : std_logic;
  signal c4 : std_logic;
  signal g0 : std_logic;
  signal p0 : std_logic;
  signal g1 : std_logic;
  signal p1 : std_logic;
  signal g2 : std_logic;
  signal p2 : std_logic;
  signal g3 : std_logic;
  signal p3 : std_logic;
begin
  c0 <= i_C0;
  
  g0 <= i_A0 and i_B0;
  p0 <= i_A0 or i_B0;

  g1 <= i_A1 and i_B1;
  p1 <= i_A1 or i_B1;

  g2 <= i_A2 and i_B2;
  p2 <= i_A2 or i_B2;

  g3 <= i_A3 and i_B3;
  p3 <= i_A3 or i_B3;

  c1 <= p0 and (g0 or c0);
  c2 <= p1 and (g1 or p0) and (g1 or g0 or c0);
  c3 <= p2 and (g2 or p1) and (g2 or g1 or p0) and (g2 or g1 or g0 or c0);
  c4 <= p3 and (g3 or p2) and (g3 or g2 or p1) and (g3 or g2 or g1 or p0)
        and (g3 or g2 or g1 or g0 or c0);

  o_C4 <= c4;
  o_S0 <= i_A0 xor i_B0 xor i_C0;
  o_S1 <= i_A1 xor i_B1 xor c1;
  o_S2 <= i_A2 xor i_B2 xor c2;
  o_S3 <= i_A3 xor i_B3 xor c3;
end architecture sn74_283_arch;