-- File : comp12bit_tb.vhd
-- Testbench for comp12.vhd
-- Author : Edson S. Gomi
-- Version : 1
-- Date : November 2017


library IEEE;
use IEEE.std_logic_1164.all;

--  A testbench has no ports.

entity comp12bit_tb is
end entity comp12bit_tb;

architecture behav of comp12bit_tb is

  --  Declaration of the component that will be instantiated.  
  component comp12bit
    port (
      XD : in std_logic_vector (11 downto 0);
      YD : in std_logic_vector (11 downto 0);
      XLTY : out std_logic;
      XEQY : out std_logic;
      XGTY : out std_logic
      );
  end component;

  signal xd : std_logic_vector (11 downto 0);
  signal yd : std_logic_vector (11 downto 0);
  signal xlty : std_logic;
  signal xeqy : std_logic;
  signal xgty : std_logic;
  
begin
  --  Component instantiation.
  ham: entity work.comp12bit port map (
    XD => xd,
    YD => yd,
    XLTY => xlty,
    XEQY => xeqy,
    XGTY => xgty
    );

  --  This process does the real job.
  stimulus_process: process is
    type pattern_type is record
      --  The inputs of the circuit.
      xd : std_logic_vector (11 downto 0);
      yd : std_logic_vector (11 downto 0);
      
      --  The expected outputs of the circuit.
      xlty : std_logic;
      xeqy : std_logic;
      xgty : std_logic;
      
    end record;

    --  The patterns to apply.
    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
      (("100000000000","010000000000",'0','0','1'),
       ("000000000001","000100000000",'1','0','0'),
       ("010000100000","000000000100",'0','0','1'),
       ("011111111111","100000000000",'1','0','0'),
       ("000100000000","000010000100",'0','0','1'),
       ("000011111000","100000000001",'1','0','0'),
       ("000000000000","000000000000",'0','1','0'));

  begin
    --  Check each pattern.
    for k in patterns'range loop
      --  Set the inputs.
      xd <= patterns(k).xd;
      yd <= patterns(k).yd;
      
  --  Wait for the results.
  wait for 5 ns;
  --  Check the outputs.

      assert xlty = patterns(k).xlty
        report "bad check xlty" severity error;
      assert xeqy = patterns(k).xeqy
        report "back check xeqy" severity error;
      assert xgty = patterns(k).xgty
        report "bad check xgty" severity error;
      
  end loop;
  assert false report "end of test" severity note;
  --  Wait forever; this will finish the simulation.
    wait;
  end process;
  end behav;