-- File : sn74_85_tb.vhd
-- Author : Edson S. Gomi
-- Version : 1
-- Date : November 2017

library IEEE;
use IEEE.std_logic_1164.all;

--  A testbench has no ports.

entity sn74_85_tb is
end entity sn74_85_tb;

architecture sn74_85_tb_arch of sn74_85_tb is

  --  Declaration of the component that will be instantiated.  
  component sn74_85
    port (
    i_A3 : in std_logic;
    i_B3 : in std_logic;
    i_A2 : in std_logic;
    i_B2 : in std_logic;
    i_A1 : in std_logic;
    i_B1 : in std_logic;
    i_A0 : in std_logic;
    i_B0 : in std_logic;
    i_AGTB : in std_logic;
    i_ALTB : in std_logic;
    i_AEQB : in std_logic;
    o_AGTB : out std_logic;
    o_ALTB : out std_logic;
    o_AEQB : out std_logic
    );
  end component;

  signal i_a3 : std_logic;  
  signal i_b3 : std_logic;
  signal i_a2 : std_logic;
  signal i_b2 : std_logic;
  signal i_a1 : std_logic;
  signal i_b1 : std_logic;
  signal i_a0 : std_logic;
  signal i_b0 : std_logic;
  signal i_agtb : std_logic;
  signal i_altb : std_logic;
  signal i_aeqb : std_logic;
  signal o_agtb : std_logic;
  signal o_altb : std_logic;
  signal o_aeqb : std_logic;
  
begin
  --  Component instantiation.
  comparator: entity work.sn74_85 port map (
    i_A3 => i_a3,
    i_B3 => i_b3,
    i_A2 => i_a2,
    i_B2 => i_b2,
    i_A1 => i_a1,
    i_B1 => i_b1,
    i_A0 => i_a0,
    i_B0 => i_b0,
    i_AGTB => i_agtb,
    i_ALTB => i_altb,
    i_AEQB => i_aeqb,
    o_AGTB => o_agtb,
    o_ALTB => o_altb,
    o_AEQB => o_aeqb
    );
  
  --  This process does the real job.
  stimulus_process: process is
    type pattern_type is record
      --  The inputs of the circuit.
  i_a3 : std_logic;  
  i_b3 : std_logic;
  i_a2 : std_logic;
  i_b2 : std_logic;
  i_a1 : std_logic;
  i_b1 : std_logic;
  i_a0 : std_logic;
  i_b0 : std_logic;
  i_agtb : std_logic;
  i_altb : std_logic;
  i_aeqb : std_logic;
       
      --  The expected outputs of the circuit.
  o_agtb : std_logic;
  o_altb : std_logic;
  o_aeqb : std_logic;

 
    end record;

    --  The patterns to apply.
    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
    -- (i_A3,i_B3, i_A2,i_B2, i_A1,i_B1, i_A0,i_B0, i_AGTB,i_ALTB,i_AEQB, o_AGTB,o_ALTB,o_AEQB) 
      (( '1', '0',  '0', '0',  '0', '0',  '0', '0',    '0',   '0',   '1',    '1',   '0',   '0'), --A3>B3 
       ( '0', '1',  '0', '0',  '0', '0',  '0', '0',    '0',   '0',   '1',    '0',   '1',   '0'), --A3<B3
       ( '0', '0',  '1', '0',  '0', '0',  '0', '0',    '0',   '0',   '1',    '1',   '0',   '0'), --A3=B3,A2>B2
       ( '0', '0',  '0', '1',  '0', '0',  '0', '0',    '0',   '0',   '1',    '0',   '1',   '0'), --A3=B3,A2<B2
       ( '0', '0',  '0', '0',  '1', '0',  '0', '0',    '0',   '0',   '1',    '1',   '0',   '0'), --A3=B3,A2=B2,A1>B1
       ( '0', '0',  '0', '0',  '0', '1',  '0', '0',    '0',   '0',   '1',    '0',   '1',   '0'), --A3=B3,A2=B2,A1<B1
       ( '0', '0',  '0', '0',  '0', '0',  '1', '0',    '0',   '0',   '1',    '1',   '0',   '0'), --A3=B3,A2-B2,A1=B1,A0>B0
       ( '0', '0',  '0', '0',  '0', '0',  '0', '1',    '0',   '0',   '1',    '0',   '1',   '0'), --A3=B3,A2=B2,A1=B1,A0<B0
       ( '0', '0',  '0', '0',  '0', '0',  '0', '0',    '1',   '0',   '0',    '1',   '0',   '0'), --A3=B3,A2=B2,A1=B1,A0=B0,AGTB
       ( '0', '0',  '0', '0',  '0', '0',  '0', '0',    '0',   '1',   '0',    '0',   '1',   '0'), --A3=B3,A2=B2,A1=B1,A0=B0,ALTB
       ( '0', '0',  '0', '0',  '0', '0',  '0', '0',    '1',   '1',   '0',    '0',   '0',   '0'), --A3=B3,A2=B2,A1=B1,A0=B0,AGTB,ALTB
       ( '0', '0',  '0', '0',  '0', '0',  '0', '0',    '0',   '0',   '0',    '1',   '1',   '0'), --A3=B3,A2=B2,A1=B1,A0=B0
       ( '0', '0',  '0', '0',  '0', '0',  '0', '0',    '0',   '0',   '1',    '0',   '0',   '1')); --A3=B3,A2=B2,A1=B1,A0=B0,AEQB
       
  begin
    
    --  Check each pattern.
    for k in patterns'range loop
      --  Set the inputs.
      i_a3 <= patterns(k).i_a3;
      i_b3 <= patterns(k).i_b3;
      i_a2 <= patterns(k).i_a2;
      i_b2 <= patterns(k).i_b2;
      i_a1 <= patterns(k).i_a1;
      i_b1 <= patterns(k).i_b1;
      i_a0 <= patterns(k).i_a0;
      i_b0 <= patterns(k).i_b0;
      i_agtb <= patterns(k).i_agtb;
      i_altb <= patterns(k).i_altb;
      i_aeqb <= patterns(k).i_aeqb;

  --  Wait for the results.
  wait for 5 ns;
  
  --  Check the outputs.
      assert o_agtb = patterns(k).o_agtb
        report "bad check o_AGTB" severity error;
      assert o_altb = patterns(k).o_altb
        report "bad check o_ALTB" severity error;
      assert o_aeqb = patterns(k).o_aeqb
        report "bad check o_AEQB" severity error;
    end loop;
    
  assert false report "end of test" severity note;
  --  Wait forever; this will finish the simulation.
    wait;
    end process;
    
end sn74_85_tb_arch;