library IEEE;
use IEEE.std_logic_1164.all;

entity vxor3 is
  port (
    A, B, C : in std_logic;
    Y : out std_logic
    );
end entity vxor3;

architecture vxor3_arch of vxor3 is
begin
  Y <= A xor B xor C;
end architecture vxor3_arch;