-- File : sn74_138.vhd
-- 3-to-8 decoder
-- Author : Edson S. Gomi
-- Version : 1
-- Date : October 2017

library IEEE;
use IEEE.std_logic_1164.all;

entity sn74_138 is
  port (
    i_G1 : in std_logic;
    i_G2A_L : in std_logic;
    i_G2B_L : in std_logic;
    i_A : in std_logic;
    i_B : in std_logic;
    i_C : in std_logic;
    o_Y0_L : out std_logic;
    o_Y1_L : out std_logic;
    o_Y2_L : out std_logic;
    o_Y3_L : out std_logic;
    o_Y4_L : out std_logic;
    o_Y5_L : out std_logic;
    o_Y6_L : out std_logic;
    o_Y7_L : out std_logic
    );
end entity sn74_138;

architecture sn74_138_arch of sn74_138 is
  signal CBA : std_logic_vector (2 downto 0);
  signal Y_L : std_logic_vector (7 downto 0);
  signal Y_L_i : std_logic_vector (7 downto 0);
begin
  CBA <= i_C & i_B & i_A;
  with CBA select Y_L_I <=
    "01111111" when "111",
    "10111111" when "110",
    "11011111" when "101",
    "11101111" when "100",
    "11110111" when "011",
    "11111011" when "010",
    "11111101" when "001",
    "11111110" when "000",
    "11111111" when others;
  Y_L <= Y_L_i when (i_G1 and not(i_G2A_L) and not(i_G2B_L)) = '1' else (others => '1');
  o_Y0_L <= Y_L(0);
  o_Y1_L <= Y_L(1);
  o_Y2_L <= Y_L(2);
  o_Y3_L <= Y_L(3);
  o_Y4_L <= Y_L(4);
  o_Y5_L <= Y_L(5);
  o_Y6_L <= Y_L(6);
  o_Y7_L <= Y_L(7);
end sn74_138_arch;