library IEEE;
use IEEE.std_logic_1164.all;

entity sn74_86 is
  port (
    i_1A : in std_logic;
    i_1B : in std_logic;
    i_2A : in std_logic;
    i_2B : in std_logic;
    i_3A : in std_logic;
    i_3B : in std_logic;
    i_4A : in std_logic;
    i_4B : in std_logic;
    o_1Y : out std_logic;
    o_2Y : out std_logic;
    o_3Y : out std_logic;
    o_4Y : out std_logic
    );
end entity sn74_86;

architecture sn74_86_arch of sn74_86 is
begin
  o_1Y <= i_1A xor i_1B;
  o_2Y <= i_2A xor i_2B;
  o_3Y <= i_3A xor i_3B;
  o_4Y <= i_4A xor i_4B;
end architecture sn74_86_arch;