-- Entity : memory.vhd -- Author: Edson S. Gomi -- Version : 1 -- Date : October 2017 library IEEE; use IEEE.std_logic_1164.all; entity memory is port ( WR : std_logic; D : in std_logic_vector (8 downto 0); Q : out std_logic_vector (8 downto 0) := (others => '1') ); end entity memory; architecture memory_arch of memory is begin p0: process (WR) is begin if (WR ='1') then Q <= D; end if; end process p0; end architecture memory_arch;