library IEEE;
use IEEE.std_logic_1164.all;

--  A testbench has no ports.

entity parity9_tb is
end entity parity9_tb;

architecture parity9_tb_arch of parity9_tb is

  --  Declaration of the component that will be instantiated.  
  component parity9
    port (
      I : in std_logic_vector (1 to 9);
      EVEN, ODD : out std_logic
      );
  end component;

  signal i : std_logic_vector (1 to 9);
  signal even, odd : std_logic;
  
begin
  --  Component instantiation.
  parity_checker: entity work.parity9 (parity9b) port map (
    I => i,
    EVEN => even,
    ODD => odd
    );
  
  --  This process does the real job.
  stimulus_process: process is
    type pattern_type is record
      --  The inputs of the circuit.
      i : std_logic_vector (1 to 9);

      --  The expected outputs of the circuit.
      even, odd : std_logic;
    end record;


    --  The patterns to apply.
    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
      (("000000000",'1','0'),
       ("000000010",'0','1'),
       ("000100001",'1','0'),
       ("001101011",'0','1'),
       ("001001000",'1','0'),
       ("100000101",'0','1'));

  begin
    --  Initialize inputs.
    i <= "111111111";

    wait for 5 ns;
    
    --  Check each pattern.
    for k in patterns'range loop
      --  Set the inputs.
  i <= patterns(k).i;
  
  --  Wait for the results.
  wait for 3 ns;
  --  Check the outputs.
  assert even = patterns(k).even
    report "bad check even" severity error;
  assert odd = patterns(k).odd
    report "bad check odd" severity error;
end loop;
  assert false report "end of test" severity note;
  --  Wait forever; this will finish the simulation.
    wait;
    end process;
    
end parity9_tb_arch;