-- Circuitos Duais -- Autor: Edson S. Gomi -- Versao 2 (Agosto de 2017) library IEEE; use IEEE.std_logic_1164.all; -- A testbench has no ports. entity dual_tb is end entity dual_tb; architecture dual_tb_arch of dual_tb is -- Declaration of the component that will be instantiated. component dual port (x1, x2, x3, x4, x5 : in std_logic; f, fdual : out std_logic); end component; signal b5,b4,b3,b2,b1 : std_logic := '0'; signal bout, boutdual : std_logic := '0'; begin -- Component instantiation. detector: entity work.dual port map ( x5 => b5, x4 => b4, x3 => b3, x2 => b2, x1 => b1, f => bout, fdual => boutdual ); -- This process does the real job. stimulus_process: process is type pattern_type is record -- The inputs of the circuit. b5,b4,b3,b2,b1 : std_logic; -- The expected outputs of the circuit. bout, boutdual : std_logic; end record; -- The patterns to apply. type pattern_array is array (natural range <>) of pattern_type; constant patterns : pattern_array := (('0','0','0','0','0','0','1'), -- 0 ('0','0','0','0','1','0','1'), -- 1 ('0','0','0','1','0','0','1'), -- 2 ('0','0','0','1','1','0','1'), -- 3 ('0','0','1','0','0','0','1'), -- 4 ('0','0','1','0','1','0','1'), -- 5 ('0','0','1','1','0','0','1'), -- 6 ('0','0','1','1','1','0','1'), -- 7 ('0','1','0','0','0','0','1'), -- 8 ('0','1','0','0','1','1','0'), -- 9 ('0','1','0','1','0','0','1'), -- 10 ('0','1','0','1','1','1','0'), -- 11 ('0','1','1','0','0','0','1'), -- 12 ('0','1','1','0','1','0','1'), -- 13 ('0','1','1','1','0','0','1'), -- 14 ('0','1','1','1','1','0','1'), -- 15 ('1','0','0','0','0','1','0'), -- 16 ('1','0','0','0','1','0','1'), -- 17 ('1','0','0','1','0','1','0'), -- 18 ('1','0','0','1','1','0','1'), -- 19 ('1','0','1','0','0','1','0'), -- 20 ('1','0','1','0','1','0','1'), -- 21 ('1','0','1','1','0','0','1'), -- 22 ('1','0','1','1','1','0','1'), -- 23 ('1','1','0','0','0','1','0'), -- 24 ('1','1','0','0','1','1','0'), -- 25 ('1','1','0','1','0','1','0'), -- 26 ('1','1','0','1','1','1','0'), -- 27 ('1','1','1','0','0','1','0'), -- 28 ('1','1','1','0','1','0','1'), -- 29 ('1','1','1','1','0','0','1'), -- 30 ('1','1','1','1','1','0','1')); -- 31 begin -- Check each pattern. for i in patterns'range loop -- Set the inputs. b1 <= patterns(i).b1; b2 <= patterns(i).b2; b3 <= patterns(i).b3; b4 <= patterns(i).b4; b5 <= patterns(i).b5; -- Wait for the results. wait for 5 ns; -- Check the outputs. assert bout = patterns(i).bout report "bad check f" severity error; assert boutdual = patterns(i).boutdual report "bad check fdual" severity error; end loop; assert false report "end of test" severity note; -- Wait forever; this will finish the simulation. wait; end process; end dual_tb_arch;