-- Alarme residencial -- Autor: Edson S. Gomi -- Versao 1 (Agosto de 2017) library IEEE; use IEEE.std_logic_1164.all; -- A testbench has no ports. entity house_alarm_tb is end entity house_alarm_tb; architecture house_alarm_tb_arch of house_alarm_tb is -- Declaration of the component that will be instantiated. component house_alarm port ( panic, enable, exiting, window, door, garage : in std_logic; alarm : out std_logic); end component; signal Panic,Enable,Exiting,Window,Door,Garage : std_logic := '0'; signal Alarm : std_logic := '0'; begin -- Component instantiation. comp_alarm: entity work.house_alarm port map ( panic => Panic, enable => Enable, exiting => Exiting, window => Window, door => Door, garage => Garage, alarm => Alarm ); -- This process does the real job. stimulus_process: process is type pattern_type is record -- The inputs of the circuit. Panic, Enable, Exiting, Window, Door, Garage : std_logic; -- The expected outputs of the circuit. Alarm : std_logic; end record; -- The patterns to apply. type pattern_array is array (natural range <>) of pattern_type; constant patterns : pattern_array := (('0','0','-','-','-','-','0'), -- Enable = '0' ('0','1','1','-','-','-','0'), -- Exiting = '1' ('0','1','0','1','1','1','0'), -- Window = '1',Door = '1', Garage = '1' ('0','1','0','0','-','-','1'), -- Window = '0' ('0','1','0','-','0','-','1'), -- Door = '0' ('0','1','0','-','-','0','1'), -- Garage = '0' ('1','-','-','-','-','-','1')); -- Panic = '1' begin -- Check each pattern. for i in patterns'range loop -- Set the inputs. Panic <= patterns(i).Panic; Enable <= patterns(i).Enable; Exiting <= patterns(i).Exiting; Window <= patterns(i).Window; Door <= patterns(i).Door; Garage <= patterns(i).Garage; -- Wait for the results. wait for 5 ns; -- Check the outputs. assert Alarm = patterns(i).Alarm report "bad check" severity error; end loop; assert false report "end of test" severity note; -- Wait forever; this will finish the simulation. wait; end process; end house_alarm_tb_arch;