Compile Verilog
(Compile -> Compile VERILOG file)The cell compiler can handle layout generation from a primitive-based VERILOG description text into a layout form automatically. Click on Compile -> Compile Verilog File. Select a VERILOG text file and click on "Generate". The list of primitives is given below.
PRIMITIVE |
NODES |
EXAMPLE |
dreg |
Inputs : Data,RESET, CLOCK Outputs: Q, nQ |
dreg reg1(d,rst,h,q,nq); |
Inv, not |
Inputs : IN Outputs: OUT |
inv inv1(s,e); // both ‘inv’ and ‘not’ not inv1(s,e); // can be used |
and |
Inputs : 2 to 4 Outputs: S |
and and1(s,a,b,c,d); // limit inputs to 4 |
nand |
Inputs : 2 to 4 Outputs: S |
nand nand1(s,a,b,c,d); |
or |
Inputs : 2 to 4 Outputs: S |
or or3(s,a,b,c); |
nor |
Inputs : 2 to 4 Outputs: S |
nor my_nor4(s,a,b,c,d); |
xor |
Inputs : a,b Outputs: S |
xor xor_gate(xor_out,d0,d1); |
Nmos |
Inputs: gate, source Outputs: drain |
nmos nmos1(d,s,g); |
[Back]