library ieee;
use ieee.std_logic_1164.all;

entity main is 
	port(a, b, c, d: in std_logic;
			x: out std_logic);
end main;

architecture arch_main of main is
	signal s1, s2, s3, s4: std_logic;
begin
	s1 <= a and b;
	s2 <= (not ((not c) and d));
	s3 <= (((not a) and b) and c);
	s4 <= (((not b) and (not c)) and (not d));
	x <= s1 or s2 or s3 or s4;
end arch_main;