library ieee;
use ieee.std_logic_1164.all;

entity main is
	port(a, b, c, d: in std_logic;
			y: out std_logic);
end main;

architecture arch_main of main is
	signal s1, s2, s3, s4, s5, s6, s7: std_logic;
begin
	s1 <= not (c or d);
	s2 <= (not a) and c;
	s3 <= s2 and (not d);
	s4 <= a and (not b);
	s5 <= s4 and (not c);
	s6 <= ((((not a) and (not b)) and c) and d);
	s7 <= ((a and c) and (not d));
	y <= s1 or s3 or s5 or s6 or s7;
end arch_main;