library ieee;
use ieee.std_logic_1164.all;

entity random is
	port(a, b, c, d, e, f, g, h, i, j, k, l: in std_logic;
			s1, s2, s3, s4, s5: out std_logic);
end random;

architecture arch_random of random is
	signal sig1, sig2, sig3, sig4, sig5, sig6, sig7: std_logic;
begin
	sig1 <= a and b;
	sig2 <= c or d;
	sig3 <= (not e) and f;
	sig4 <= g nand h;
	sig5 <= i nor j;
	sig6 <= k xor l;
	sig7 <= (not sig6) and sig2;
	s1 <= sig1 nand (not sig2);
	s2 <= sig3 or sig4;
	s3 <= sig5 xor sig6;
	s4 <= not sig7;
	s5 <= sig4 and sig1;
end arch_random;