library ieee;
use ieee.std_logic_1164.all;

entity portas_logicas is
	port(a, b : in std_logic;
			c, d, e, f, g, h: out std_logic);
end portas_logicas;

architecture arch_portas of portas_logicas is
begin
	c <= a and b;
	d <= a or b;
	e <= not a;
	f <= a nand b;
	g <=  a nor b;
	h <=  a xor b;
end arch_portas;