-- Quartus VHDL Template
-- Clearable loadable enablable counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY __entity_name IS

	PORT
	(
		__data_input_name	: IN	INTEGER RANGE 0 TO __count_value;
		__clk_input_name	: IN	STD_LOGIC;
		__clrn_input_name	: IN	STD_LOGIC;
		__ena_input_name	: IN	STD_LOGIC;
		__ld_input_name		: IN	STD_LOGIC;
		__count_output_name	: OUT	INTEGER RANGE 0 TO __count_value
	);
	
END __entity_name;

ARCHITECTURE a OF __entity_name IS

	SIGNAL	__count_signal_name	: INTEGER RANGE 0 TO __count_value;
	
BEGIN

	PROCESS (__clk_input_name, __clrn_input_name)
	BEGIN
	
		IF __clrn_input_name = '0' THEN
		
			__count_signal_name <= 0;
			
		ELSIF (__clk_input_name'EVENT AND __clk_input_name = '1') THEN
			
			IF __ld_input_name = '1' THEN
					
				__count_signal_name <= __data_input_name;
					
			ELSE
			
				IF __ena_input_name = '1' THEN

					__count_signal_name <= __count_signal_name + 1;
				
				ELSE

					__count_signal_name <= __count_signal_name;
					
				END IF;
				
			END IF;
			
		END IF;
		
	END PROCESS;

	__count_output_name <= __count_signal_name;
	
END a;